| 1 | /* |
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| 2 | * 2nd - OMAP "second stage" tt-loader |
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| 3 | * |
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| 4 | * Copyright (C) 2008 Guillaume Bougard <gbougard@pkg.fr> |
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| 5 | * Copyright (C) 2005 Luis Recuerda <lrec@helios.homeip.net> |
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| 6 | * |
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| 7 | * This program is free software; you can redistribute it and/or |
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| 8 | * modify it under the terms of the GNU General Public License |
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| 9 | * as published by the Free Software Foundation; either version 2 |
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| 10 | * of the License, or (at your option) any later version. |
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| 11 | * |
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| 12 | * This program is distributed in the hope that it will be useful, |
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| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | * GNU General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with this program; if not, write to the Free Software |
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| 19 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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| 20 | * |
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| 21 | */ |
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| 22 | |
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| 23 | .equ WATCHDOG_VAL1, 0xf5 |
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| 24 | .equ WATCHDOG_VAL2, 0xa0 |
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| 25 | |
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| 26 | .code 32 |
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| 27 | |
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| 28 | _vectors: |
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| 29 | |
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| 30 | .extern bend |
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| 31 | |
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| 32 | .word _start-_vectors |
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| 33 | .word bend-_start |
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| 34 | .word 0, 0, 0 |
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| 35 | .word 0x00444e32 |
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| 36 | .word 0, 0 |
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| 37 | .word 0xffffffff |
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| 38 | .word 0xffffffff |
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| 39 | .word 0xffffffff |
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| 40 | .word 0xffffffff |
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| 41 | .word 0xffffffff |
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| 42 | .word 0xffffffff |
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| 43 | .word 0xffffffff |
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| 44 | .word 0xffffffff |
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| 45 | |
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| 46 | .global _start |
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| 47 | _start: |
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| 48 | /* |
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| 49 | * set the cpu to SVC32 mode as in x-load |
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| 50 | */ |
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| 51 | mrs r0, cpsr |
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| 52 | bic r0, r0, #0x1f |
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| 53 | orr r0, r0, #0xd3 |
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| 54 | msr cpsr, r0 |
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| 55 | |
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| 56 | // Turn off the watchdog during init... |
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| 57 | ldr r0, REG_WDT_TIMER_MODE |
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| 58 | mov r1, #WATCHDOG_VAL1 |
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| 59 | str r1, [r0] |
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| 60 | mov r1, #WATCHDOG_VAL2 |
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| 61 | str r1, [r0] |
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| 62 | |
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| 63 | // Mask all IRQs by setting all bits in the INTMR default |
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| 64 | mov r1, #0xffffffff |
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| 65 | ldr r0, REG_IHL1_MIR |
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| 66 | str r1, [r0] |
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| 67 | ldr r0, REG_IHL2_MIR |
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| 68 | str r1, [r0] |
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| 69 | |
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| 70 | // flush v4 I/D caches |
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| 71 | mov r0, #0 |
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| 72 | mcr p15, 0, r0, c7, c7, 0 // flush v3/v4 cache |
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| 73 | mcr p15, 0, r0, c8, c7, 0 // flush v4 TLB |
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| 74 | |
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| 75 | // disable MMU stuff and caches |
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| 76 | mrc p15, 0, r0, c1, c0, 0 |
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| 77 | bic r0, r0, #0x00002300 // clear bits 13, 9:8 (--V- --RS) |
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| 78 | bic r0, r0, #0x00000087 // clear bits 7, 2:0 (B--- -CAM) |
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| 79 | orr r0, r0, #0x00000002 // set bit 2 (A) Align |
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| 80 | orr r0, r0, #0x00001000 // set bit 12 (I) I-Cache |
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| 81 | mcr p15, 0, r0, c1, c0, 0 |
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| 82 | |
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| 83 | ldr r0, REG_WSPR |
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| 84 | ldr r1, WSPR_VAL1 |
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| 85 | str r1, [r0] |
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| 86 | ldr r2, REG_WWPS |
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| 87 | |
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| 88 | watch1Wait: |
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| 89 | ldr r1, [r2] |
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| 90 | tst r1, #0x10 |
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| 91 | bne watch1Wait |
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| 92 | |
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| 93 | ldr r1, WSPR_VAL2 |
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| 94 | str r1, [r0] |
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| 95 | watch2Wait: |
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| 96 | ldr r1, [r2] |
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| 97 | tst r1, #0x10 |
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| 98 | bne watch2Wait |
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| 99 | |
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| 100 | ldr sp, _stack |
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| 101 | |
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| 102 | .extern _main |
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| 103 | bl _main |
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| 104 | |
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| 105 | WSPR_VAL1: |
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| 106 | .word 0x0000aaaa |
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| 107 | WSPR_VAL2: |
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| 108 | .word 0x00005555 |
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| 109 | |
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| 110 | REG_IHL1_MIR: // 32 bits |
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| 111 | .word 0xfffecb04 |
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| 112 | REG_IHL2_MIR: // 32 bits |
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| 113 | .word 0xfffe0004 |
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| 114 | REG_WDT_TIMER_MODE: // 16 bits |
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| 115 | .word 0xfffec808 |
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| 116 | REG_WSPR: |
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| 117 | .word 0xfffeb048 |
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| 118 | REG_WWPS: |
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| 119 | .word 0xfffeb034 |
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| 120 | |
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| 121 | _stack: |
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| 122 | .word 0x2000F000 |
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