source: tt-loader/2nd/start.S @ 15

Last change on this file since 15 was 12, checked in by guillaume, 14 years ago

Publication tt-loader v0.2

File size: 2.6 KB
Line 
1/*
2 * 2nd - OMAP "second stage" tt-loader
3 *
4 * Copyright (C) 2008 Guillaume Bougard <gbougard@pkg.fr>
5 * Copyright (C) 2005 Luis Recuerda <lrec@helios.homeip.net>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
20 *
21 */
22
23.equ WATCHDOG_VAL1, 0xf5
24.equ WATCHDOG_VAL2, 0xa0
25
26        .code 32
27
28_vectors:
29
30        .extern bend
31
32.word   _start-_vectors
33.word   bend-_start
34.word   0, 0, 0
35.word   0x00444e32
36.word   0, 0
37.word   0xffffffff
38.word   0xffffffff
39.word   0xffffffff
40.word   0xffffffff
41.word   0xffffffff
42.word   0xffffffff
43.word   0xffffffff
44.word   0xffffffff
45
46        .global _start
47_start:
48        /*
49         * set the cpu to SVC32 mode as in x-load
50         */
51        mrs r0, cpsr
52        bic r0, r0, #0x1f
53        orr r0, r0, #0xd3
54        msr cpsr, r0
55
56        // Turn off the watchdog during init...
57        ldr r0, REG_WDT_TIMER_MODE
58        mov r1, #WATCHDOG_VAL1
59        str r1, [r0]
60        mov r1, #WATCHDOG_VAL2
61        str r1, [r0]
62
63        // Mask all IRQs by setting all bits in the INTMR default
64        mov r1, #0xffffffff
65        ldr r0, REG_IHL1_MIR
66        str r1, [r0]
67        ldr r0, REG_IHL2_MIR
68        str r1, [r0]
69
70        // flush v4 I/D caches
71        mov r0, #0
72        mcr p15, 0, r0, c7, c7, 0   // flush v3/v4 cache
73        mcr p15, 0, r0, c8, c7, 0   // flush v4 TLB
74
75        // disable MMU stuff and caches
76        mrc p15, 0, r0, c1, c0, 0
77        bic r0, r0, #0x00002300     // clear bits 13, 9:8 (--V- --RS)
78        bic r0, r0, #0x00000087     // clear bits 7, 2:0 (B--- -CAM)
79        orr r0, r0, #0x00000002     // set bit 2 (A) Align
80        orr r0, r0, #0x00001000     // set bit 12 (I) I-Cache
81        mcr p15, 0, r0, c1, c0, 0
82
83        ldr r0, REG_WSPR
84        ldr r1, WSPR_VAL1
85        str r1, [r0]
86        ldr     r2, REG_WWPS
87
88watch1Wait:
89        ldr     r1, [r2]
90        tst     r1, #0x10
91        bne     watch1Wait
92
93        ldr r1, WSPR_VAL2
94        str r1, [r0]
95watch2Wait:
96        ldr r1, [r2]
97        tst r1, #0x10
98        bne watch2Wait
99
100        ldr sp, _stack
101
102        .extern _main
103        bl _main
104
105WSPR_VAL1:
106        .word 0x0000aaaa
107WSPR_VAL2:
108        .word 0x00005555
109
110REG_IHL1_MIR:                   // 32 bits
111        .word 0xfffecb04
112REG_IHL2_MIR:                   // 32 bits
113        .word 0xfffe0004
114REG_WDT_TIMER_MODE:                             // 16 bits
115        .word 0xfffec808
116REG_WSPR:
117        .word 0xfffeb048
118REG_WWPS:
119        .word 0xfffeb034
120
121_stack:
122        .word   0x2000F000
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